CompOrg at NCKU EE
Exploring Cache Behavior under Ideal Memory: Understanding Data Locality
15
Implement A Configurable Cache in SystemVerilog
Preface
Building A Functional RISC-V ISA Simulator
1
What is Computer?
2
Introduction to RISC-V ISA
3
Design A Simple ISA Simulator
4
Lab 1 Assignment
RISC-V Assembly and Bare-Metal Programming
5
RISC-V Assembly Programming
6
Bare-metal Programming and Runtime Environment
7
Lab 2 Assignment
Single-Cycle CPU Micro-Architecture Design and Reference-Model-Based Verification
8
Single-Cycle CPU Micro-architecture Design
9
Reference-Model-Based Verification
Pipeline CPU Micro-Architecture Design
10
Fundamental and Motivation of Pipelining
11
Pipeline CPU Micro-Architecture Design
Exploring Cache Behavior under Ideal Memory: Understanding Data Locality
12
Principle of Locality
13
Cache Organization
14
Cache Performance and Profiling
15
Implement A Configurable Cache in SystemVerilog
A More Realistic System: Non-ideal Main Memory with Abstract DRAM Model
16
Abstract DRAM Behavior and Modeling
17
Integrate DRAM C Model into our RTL System Design
References
Appendices
Review of C Programming
A
Pointers in C
B
Object-Oriented Programming in Pure C
On-Chip System Bus and AXI Protocol
C
Introduction to AMBA AXI Bus Protocol
D
PULP-Platform AXI Implementation
E
Design A AXI4-Lite Wrapper for Some Devices
RTL Programming Guides
F
Introduction to Verilog
G
Introduction to SystemVerilog
H
SystemVerilog Assertion (SVA)
I
Linux Commandline Tutorial
J
Version Control System: Git
K
How To Use Docker
Exploring Cache Behavior under Ideal Memory: Understanding Data Locality
15
Implement A Configurable Cache in SystemVerilog
15
Implement A Configurable Cache in SystemVerilog
14
Cache Performance and Profiling
A More Realistic System: Non-ideal Main Memory with Abstract DRAM Model