Pipeline CPU Micro-Architecture Design

In Lab 4, the goal of this lab is to examine:

• the limitations and impractical aspects of a Single-Cycle CPU
• the Critical Timing Path issue

To overcome these problems, we will explore and design a pipelined CPU micro-architecture. By the end of this lab, you will gain a deeper understanding of CPU micro-architecture design, the pipelining process, and the data hazard issues that may arise.

This figure is from [1]

[1]

J.-L. Baer, Microprocessor architecture: From simple pipelines to chip multiprocessors. Cambridge University Press, 2009.