Building A Functional RISC-V ISA Simulator

In Lab 1, our mission is to build a functional simulator that can emulate a simple RISC-V machine. To understand how to construct such a simulator, we must examine three key concepts:

• What a computer is
• What so called Software/Hardware Interface — ISA is, and what RISC-V is
• How to use C language to build a simple RISC-V simulator

By the end of this lab, you should be able to implement a simulator capable of decoding and executing most of the basic RV32I instructions. In the process, you will also develop a solid understanding of fundamental computer concepts, as well as the RISC-V ISA.

This figure is from [1]

[1]

D. A. Patterson and J. L. Hennessy, Computer Organization and Design RISC-V Edition: The Hardware Software Interface, 1st ed. San Francisco, CA, USA: Morgan Kaufmann Publishers Inc., 2017.